The back end of line (BEOL) processes in semiconductor fabrication consist of interconnecting individual devices (e.g., transistors, capacitors, resistors, etc.) to metallization features. More specifically, BEOL typically includes the formation or deposition of contacts, insulating layers (e.g., dielectrics), metal levels, and bonding sites for chip-to-package connections.
The challenge of BEOL schemes is how to isolate metal lines from cross talk and RC delay during normal device operation, particularly in smaller technology nodes. Currently, PECVD ultra low-k dielectric (ULK) materials act as barrier to prevent EMF cross talk between metal lines. Some of the most challenging issues about using the ULK and/or nano-porous materials is that the industry is approaching the limits of creating materials for lower dielectrics (i.e., k=2.2 and lower). In fact, currently there is no stable material lower than k=2.1. And, even if it is possible to synthesize the material below k=2.2, it is very unstable, weak and prone to leakage.